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K9L8G08U1A K9G4G08U0A K9G4G08B0A
Preliminary FLASH MEMORY
K9XXG08XXA
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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K9L8G08U1A K9G4G08U0A K9G4G08B0A
Preliminary FLASH MEMORY
Document Title 512M x 8 Bit / 1G x 8 Bit NAND Flash Memory Revision History
Revision No
0.0 0.1
History
1. Initial issue 1. Add 2.7V part 2. Add note of command set table 3. Add nWP timing guide 4. Endurance 10K -> 5K
Draft Date
May. 2nd 2006 Sep. 25st 2006
Remark
Advance Preliminary
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.
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K9L8G08U1A K9G4G08U0A K9G4G08B0A
Preliminary FLASH MEMORY
512M x 8 Bit / 1G x 8 Bit NAND Flash Memory
PRODUCT LIST
Part Number K9G4G08B0A K9G4G08U0A-P K9G4G08U0A-I K9L8G08U1A-I 2.7V ~ 3.6V Vcc Range 2.5V ~ 2.9V X8 Organization PKG Type MCP(TBD) TSOP1 52ULGA
FEATURES
* Voltage Supply - 2.7V Device(K9G4G08B0A) : 2.5V ~ 2.9V - 3.3V Device(K9G4G08U0A) : 2.7V ~ 3.6V * Organization - Memory Cell Array : (512M + 16M) x 8bit - Data Register : (2K + 64) x 8bit * Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (256K + 8K)Byte * Page Read Operation - Page Size : (2K + 64)Byte - Random Read : 60s(Max.) - Serial Access : 30ns(Min.) * Memory Cell : 2bit / Memory Cell * Fast Write Cycle Time - Program time : 800s(Typ.) - Block Erase Time : 1.5ms(Typ.) * Command/Address/Data Multiplexed I/O Port * Hardware Data Protection - Program/Erase Lockout During Power Transitions * Reliable CMOS Floating-Gate Technology - Endurance : 5K Program/Erase Cycles(with 4bit/512byte ECC) - Data Retention : 10 Years * Command Register Operation * Unique ID for Copyright Protection * Package : - K9G4G08U0A-PCB0/PIB0 : Pb-FREE PACKAGE 48 - Pin TSOP1(12 x 20 / 0.5 mm pitch) - K9G4G08U0A-ICB0/IIB0 52 - Pin ULGA (12 x 17 / 1.00 mm pitch) - K9L8G08U1A-ICB0/IIB0 52 - Pin ULGA (12 x 17 / 1.00 mm pitch) - K9G4G08B0A : MCP(TBD)
GENERAL DESCRIPTION
Offered in 512Mx8bit, the K9G4G08X0A is a 4G-bit NAND Flash Memory with spare 128M-bit. The device is offered in 2.7V and 3.3V Vcc. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation can be performed in typical 800s on the 2,112-byte page and an erase operation can be performed in typical 1.5ms on a (256K+8K)byte block. Data in the data register can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9G4G08X0As extended reliability of 5K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9G4G08X0A is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
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K9L8G08U1A K9G4G08U0A K9G4G08B0A
PIN CONFIGURATION (TSOP1)
K9G4G08U0A-PCB0/PIB0
N.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C
Preliminary FLASH MEMORY
48-pin TSOP1 Standard Type 12mm x 20mm
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP1 - 1220AF
Unit :mm/Inch
0.10 MAX 0.004 #48 ( 0.25 ) 0.010 12.40 0.488 MAX #24 #25 1.000.05 0.0390.002 0.25 0.010 TYP 18.400.10 0.7240.004
+0.075
20.000.20 0.7870.008
0.20 -0.03
+0.07
#1
0.008-0.001
0.16 -0.03
+0.07
+0.003
0.50 0.0197
12.00 0.472
0.05 0.002 MIN
0.125 0.035
0~8
0.45~0.75 0.018~0.030
( 0.50 ) 0.020
4
+0.003 0.005-0.001
1.20 0.047MAX
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K9L8G08U1A K9G4G08U0A K9G4G08B0A
PIN CONFIGURATION (ULGA)
K9G4G08U0A-ICB0/IIB0
A
NC
Preliminary FLASH MEMORY
B
C
D
E
NC
F
G
H
J
K
NC
L
M
N
NC
NC
NC
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NC /RE Vcc /CE NC NC Vss NC ALE NC NC NC NC R/B NC Vss NC IO0 /WP NC IO1 NC NC NC IO7 IO6 NC IO5 IO4 NC Vcc NC NC
6 5 4 3 2 1
NC NC CLE
/WE
IO2 IO3
Vss Vss NC NC
NC
NC NC
PACKAGE DIMENSIONS
52-ULGA (measured in millimeters) Top View Bottom View
12.000.10 10.00 1.00 1.00 6 5 4 3 2 1.00 1 1.30
A B
2.00 12.000.10 7 1.00
(Datum A)
#A1
A B C D
17.000.10
F G
J K L M N
1.00
H
12-1.000.05 0.1 M C AB
41-0.700.05
0.1
M C AB
17.000.10
0.10 C
5
0.65(Max.)
Side View
0.50
2.00
1.00 2.50
12.00 17.000.10
E
1.00 2.50
(Datum B)
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K9L8G08U1A K9G4G08U0A K9G4G08B0A
Preliminary FLASH MEMORY
K9L8G08U1A-ICB0/IIB0
A
NC
B
C
D
E
NC
F
G
H
J
K
NC
L
M
N
NC
NC
NC
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NC /RE1 Vcc /CE1 /CE2 CLE2 /RE2 R/B1 R/B2 Vss /WP2 IO0-1 IO7-2 IO6-2 IO5-2 Vcc IO4-2 NC
6 5 4 3 2 1
NC NC
IO7-1 IO6-1
IO5-1 IO4-1
CLE1 Vss
/WE1 /WP1
IO2-1 IO3-1
Vss Vss IO2-2 NC
IO3-2
ALE2 ALE1
IO1-1 IO0-2
/WE2 NC
IO1-2 NC
NC NC
NC
PACKAGE DIMENSIONS
52-ULGA (measured in millimeters) Top View Bottom View
12.000.10 10.00 1.00 1.00 6 5 4 3 2 1.00 1 1.30
A B
2.00 12.000.10 7 1.00
(Datum A)
#A1
A B C D
17.000.10
F G
J K L M N
1.00
H
12-1.000.05 0.1 M C AB
41-0.700.05
0.1
M C AB
17.000.10
0.10 C
6
0.65(Max.)
Side View
0.50
2.00
1.00 2.50
12.00 17.000.10
E
1.00 2.50
(Datum B)
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K9L8G08U1A K9G4G08U0A K9G4G08B0A
PIN DESCRIPTION
Pin Name I/O0 ~ I/O7 Pin Function
Preliminary FLASH MEMORY
DATA INPUTS/OUTPUTS The I/O pins are used to input command, address and data, and to output data during read operations. The I/ O pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. ADDRESS LATCH ENABLE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high. CHIP ENABLE The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase operation. Regarding CE control during read operation, refer to 'Page read' section of Device operation. READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WRITE ENABLE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. WRITE PROTECT The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low. READY/BUSY OUTPUT The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. POWER VCC is the power supply for device. GROUND NO CONNECTION Lead is not internally connected.
CLE
ALE
CE
RE
WE
WP
R/B
Vcc Vss N.C
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected.
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K9L8G08U1A K9G4G08U0A K9G4G08B0A
Figure 1-1. K9G4G08X0A Functional Block Diagram
VCC VSS A12 - A29 X-Buffers Latches & Decoders Y-Buffers Latches & Decoders 4,096M + 128M Bit NAND Flash ARRAY
Preliminary FLASH MEMORY
A0 - A11
(2,048 + 64)Byte x 262,144
Data Register & S/A Y-Gating Command Command Register I/O Buffers & Latches VCC VSS I/0 0
CE RE WE
Control Logic & High Voltage Generator
Global Buffers
Output Driver
I/0 7 CLE ALE WP
Figure 2-1. K9G4G08X0A Array Organization
1 Block = 128 Pages (256K + 8K) Byte
256K Pages (=2,048 Blocks) 8 bit 2K Bytes 64 Bytes
1 Page = (2K + 64)Bytes 1 Block = (2K + 64)B x 128 Pages = (256K + 8K) Bytes 1 Device = (2K+64)B x 128Pages x 2,048 Blocks = 4,224 Mbits
Page Register
2K Bytes I/O 0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle A0 A8 A12 A20 A28 I/O 1 A1 A9 A13 A21 A29 I/O 2 A2 A10 A14 A22 *L 64 Bytes I/O 3 A3 A11 A15 A23 *L
I/O 0 ~ I/O 7
I/O 4 A4 *L A16 A24 *L
I/O 5 A5 *L A17 A25 *L
I/O 6 A6 *L A18 A26 *L
I/O 7 A7 *L A19 A27 *L Column Address Column Address Row Address Row Address
Row Address
NOTE : Column Address : Starting Address of the Register. * L must be set to "Low". * The device ignores any additional input of address cycles than required.
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K9L8G08U1A K9G4G08U0A K9G4G08B0A
Product Introduction
Preliminary FLASH MEMORY
The K9G4G08X0A is a 4,224Mbit(4,429,185,024bit) memory organized as 262,144 rows(pages) by 2,112x8 columns. Spare 64 columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays for accommodating data transfer between the I/O buffers and memory cells during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structured strings. A NAND structure consists of 32 cells. A cell has 2-bit data. Total 1,081,344 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 2,048 separately erasable 256K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9G4G08X0A. The K9G4G08X0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 528M-byte physical space requires 30 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase operation, however, only three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9G4G08X0A.
Table 1. Command Sets
Function Read Two-Plane Read Read ID Reset Page Program Two-Plane Page Program (2) Block Erase Two-Plane Block Erase Random Data Input(1) Random Data Output
(1)
1st Cycle 00h 60h----60h 90h FFh 80h 80h----11h 60h 60h----60h 85h 05h 00h----05h 70h F1h
2nd Cycle 30h 30h 10h 81h----10h D0h D0h E0h E0h -
Acceptable Command during Busy
O
Two Plane Random Data Output(3) Read Status 1 Read Status 2
O O
NOTE : 1. Random Data Input/Output can be executed in a page. 2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh. 3. Two-Plane Random Data Output msut be used after Two-Plane Read operation. Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
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K9L8G08U1A K9G4G08U0A K9G4G08B0A
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol VCC Voltage on any pin relative to VSS VIN VI/O Temperature Under Bias K9XXG08XXA-XCB0 K9XXG08XXA-XIB0 Storage Temperature Short Circuit Current K9XXG08XXA-XCB0 K9XXG08XXA-XIB0 Ios TSTG TBIAS
Preliminary FLASH MEMORY
Rating -0.6 to + 4.6 -0.6 to + 4.6 -0.6 to Vcc+0.3 (<4.6V) -10 to +125 -40 to +125 -65 to +150 5 C mA C V Unit
NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9XXG08XXA-XCB0 :TA=0 to 70C, K9XXG08XXA-XIB0:TA=-40 to 85C) Parameter Supply Voltage Supply Voltage Symbol VCC VSS K9G4G08B0A(2.7V) Min 2.5 0 Typ. 2.7 0 Max 2.9 0 K9G4G08U0A(3.3V) Min 2.7 0 Typ. 3.3 0 Max 3.6 0 Unit V V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
K9G4G08X0A Parameter Symbol Test Conditions Min Page Read with Operating Serial Access Current Program Erase Stand-by Current(TTL) Stand-by Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage, All inputs Output High Voltage Level Output Low Voltage Level ICC1 ICC2 ICC3 ISB1 ISB2 ILI ILO VIH* VIL* VOH VOL IOL(R/B) tRC=50ns, CE=VIL IOUT=0mA CE=VIH, WP=PRE=0V/VCC CE=VCC-0.2, WP=PRE=0V/VCC VIN=0 to Vcc(max) VOUT=0 to Vcc(max) K9G4G08B0A :IOH=-100A K9G4G08U0A :IOH=-400A K9G4G08B0A :IOL=100uA K9G4G08U0A :IOL=2.1mA K9G4G08B0A :VOL=0.1V K9G4G08U0A :VOL=0.4V VCC -0.4 -0.3 VCC -0.4 3 2.7V Typ 15 15 15 10 4 Max 30 30 30 1 50 10 10 VCC +0.3 0.5 0.4 Min 2.0 -0.3 2.4 8 3.3V Typ 15 15 15 10 10 Max 30 30 30 1 50 10 10 VCC +0.3 0.8 V 0.4 mA A mA Unit
Output Low Current(R/B)
NOTE : 1. VIL can undershoot to -0.4V and VIH can overshoot to VCC + 0.4V for durations of 20 ns or less. 2. Typical value is measured at Vcc=2.7V/3.3V, TA=25C. Not 100% tested. 3. The typical value of the K9L8G08U1A's ISB2 is 20A and the maximum value is 100A.
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K9L8G08U1A K9G4G08U0A K9G4G08B0A
VALID BLOCK
Parameter K9G4G08X0A K9L8G08U1A* Symbol NVB NVB Min 1,998 3,996 Typ. -
Preliminary FLASH MEMORY
Max 2,048 4,096 Unit Blocks Blocks
NOTE : 1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of initial invalid blocks. 2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment. 3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations. * : Each K9G4G08U0A chip in the K9L8G08U1A has Maximun 50 invalid blocks.
AC TEST CONDITION
(K9XXG08XXA-XCB0 :TA=0 to 70C, K9XXG08XXA-XIB0:TA=-40 to 85C, K9XXG08BXA: Vcc=2.5V~2.9V, K9XXG08UXA: Vcc=2.7V~3.6V unless otherwise) Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load K9G4G08B0A 0V to Vcc 5ns Vcc/2 1 TTL GATE and CL=30pF K9XXG08UXA 0V to Vcc 5ns Vcc/2 1 TTL GATE and CL=50pF
CAPACITANCE(TA=25C, VCC=2.7V/3.3V, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance Symbol CI/O CIN Test Condition VIL=0V VIN=0V Min Max 10 10 Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE H L H L L L X X X X X ALE L H L H L L X X X X(1) X CE L L L L L L X X X X H H X X X X X H X X X X WE RE H H H H H WP X X H H H X X H H L 0V/VCC(2) Data Input Data Output During Read(Busy) During Program(Busy) During Erase(Busy) Write Protect Stand-by Write Mode Read Mode Mode Command Input Address Input(5clock) Command Input Address Input(5clock)
NOTE : 1. X can be VIL or VIH. 2. WP should be biased to CMOS high or CMOS low for standby.
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Program / Erase Characteristics
Parameter Program Time Dummy Busy Time for Multi Plane Program Number of Partial Program Cycles in the Same Page Block Erase Time Symbol tPROG tDBSY Nop tBERS Min Typ 0.8 0.5 1.5
Preliminary FLASH MEMORY
Max 3 1 1 10 Unit ms s cycle ms
NOTE 1. Typical value is measured at Vcc=3.3V, TA=25C. Not 100% tested. 2. Typical Program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and 25C temperature. 3. Within a same block, program time(tPROG) of page group A is faster than that of page group B. Typical tPROG is the average program time of the page group A and B(Table 2). Page Group A: Page 0, 1, 2, 3, 6, 7, 10, 11, ... , 110, 111, 114, 115, 118, 119, 122, 123 Page Group B: Page 4, 5, 8, 9, 12, 13, 16, 17, ... , 116, 117, 120, 121, 124, 125, 126, 127
AC Timing Characteristics for Command / Address / Data Input
Parameter CLE Setup Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time Address to Data Loading Time Symbol tCLS
(1)
Min 15 5 20 5 15 15 5 15 5 30 10 100
(2)
Max -
Unit ns ns ns ns ns ns ns ns ns ns ns ns
tCLH tCS
(1)
tCH tWP tALS(1) tALH tDS
(1)
tDH tWC tWH tADL
(2)
NOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low. 2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
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K9L8G08U1A K9G4G08U0A K9G4G08B0A
AC Characteristics for Operation
Parameter Data Transfer from Cell to Register ALE to RE Delay CLE to RE Delay Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time CE Access Time RE High to Output Hi-Z CE High to Output Hi-Z CE High to ALE or CLE Don't Care RE High to Output Hold RE Low to Output Hold CE High to Output Hold RE High Hold Time Output Hi-Z to RE Low RE High to WE Low WE High to RE Low Device Resetting Time(Read/Program/Erase) Symbol tR tAR tCLR tRR tRP tWB tRC tREA tCEA tRHZ tCHZ tCSD tRHOH tRLOH tCOH tREH tIR tRHW tWHR tRST Min 10 10 20 15 30 10 15 5 15 10 0 100 60 -
Preliminary FLASH MEMORY
Max 60 100 20 25 100 30 5/10/500(1)
Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5s.
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K9L8G08U1A K9G4G08U0A K9G4G08B0A
NAND Flash Technical Notes
Initial Invalid Block(s)
Preliminary FLASH MEMORY
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment.
Identifying Initial Invalid Block(s)
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that the last page of every initial invalid block has non-FFh data at the column address of 2,048.The initial invalid block information is also erasable in most cases, and it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the initial invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
*
Create (or update) Initial Invalid Block(s) Table No
Check "FFh" at the column address 2048 of the last page in the block
Check "FFh" ?
Yes No
Last Block ?
Yes
End
Figure 3. Flow chart to create initial invalid block table.
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K9L8G08U1A K9G4G08U0A K9G4G08B0A
NAND Flash Technical Notes (Continued)
Error in write or read operation
Preliminary FLASH MEMORY
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data. Block replacement should be done upon erase or program error.
Failure Mode Write Read Erase Failure Program Failure Up to Four Bit Failure
Detection and Countermeasure sequence Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Verify ECC -> ECC Correction
ECC
: Error Correcting Code --> RS Code etc. Example) 4bit correction / 512-byte
Program Flow Chart
Start
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
I/O 6 = 1 ? or R/B = 1 ? Yes No I/O 0 = 0 ?
No
*
Program Error
Yes Program Completed
*
: If program operation results in an error, map out the block including the page in error and copy the target data to another block.
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K9L8G08U1A K9G4G08U0A K9G4G08B0A
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Start Write 60h Write Block Address Write D0h Read Status Register
Preliminary FLASH MEMORY
Read Flow Chart
Start Write 00h Write Address Write 30h Read Data ECC Generation I/O 6 = 1 ? or R/B = 1 ? Yes No No Reclaim the Error
Verify ECC Yes Page Read Completed
*
Erase Error
No
I/O 0 = 0 ? Yes Erase Completed
*
: If erase operation results in an error, map out the failing block and replace it with another block.
Block Replacement
1st (n-1)th nth (page)
{ {
Block A
1st (n-1)th nth (page)
* Step1 When an error happens in the nth page of the Block 'A' during erase or program operation. * Step2 Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block 'B') * Step3 Then, copy the nth page data of the Block 'A' in the buffer memory to the nth page of the Block 'B'. * Step4 Do not erase or program to Block 'A' by creating an 'invalid block' table or other appropriate scheme.

1 an error occurs. Buffer memory of the controller. Block B 2
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NAND Flash Technical Notes (Continued)
Addressing for program operation
Preliminary FLASH MEMORY
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant bit) page of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB page doesn't need to be page 0.
Page 127
(128)
:
Page 127
(128)
:
Page 31
(32)
:
Page 31
(1)
:
Page 2 Page 1 Page 0
(3) (2) (1)
Page 2 Page 1 Page 0
(3) (32) (2)
Data register
Data register
From the LSB page to MSB page DATA IN: Data (1) Data (128)
Ex.) Random page program (Prohibition) DATA IN: Data (1) Data (128)
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System Interface Using CE don't-care.
Preliminary FLASH MEMORY
For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,112byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of -seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption.
Figure 4. Program Operation with CE don't-care.
CLE
CE don't-care
CE
WE ALE I/Ox
80h
Address(5Cycles)
Data Input
Data Input
10h
tCS CE
tCH CE
tCEA
tREA tWP WE I/O0~7 out RE
Figure 5. Read Operation with CE don't-care.
CLE
CE don't-care
CE
RE ALE R/B tR
WE I/Ox
00h
Address(5Cycle)
30h
Data Output(serial access)
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NOTE
Preliminary FLASH MEMORY
DATA ADDRESS Col. Add1 A0~A7 Col. Add2 A8~A11 Row Add1 A12~A19 Row Add2 A20~A27 Row Add3 A28~A29
Device K9G4G08X0A
I/O I/Ox I/O 0 ~ I/O 7
Data In/Out ~2,112byte
Command Latch Cycle
CLE tCLS tCS CE tCLH tCH
tWP WE
tALS ALE tDS I/Ox
tALH
tDH
Command
Address Latch Cycle
tCLS
CLE
CE
tCS
tWC
tWC
tWC
tWC
tWP WE tALS ALE tDS I/Ox tDH tWH tALH
tWP tWH tALS tALH
tWP tWH tALH
tWP tWH tALH tALH
tALS
tALS
tALS
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
Col. Add1
Col. Add2
Row Add1
Row Add2
Row Add3
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Input Data Latch Cycle
tCLH
Preliminary FLASH MEMORY
CLE
tCH CE
ALE
tALS
tWC
tWP WE tDS I/Ox tWH tDH
tWP
tDH
tWP tDH tDS tDS
DIN 0 DIN 1 DIN final tRC
* Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)
CE
tREH RE tRHZ(1)
tCHZ(1) tREA tCOH
tREA
tREA
tRHZ(1) tRHOH(2)
I/Ox tRR R/B
Dout
Dout
Dout
NOTES : 1. Transition is measured at 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 2. tRHOH starts to be valid when frequency is lower than 20MHz.
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Preliminary FLASH MEMORY
Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L)
tRC tRP RE tREA tCEA I/Ox tRR tREA tRLOH(2) Dout tREH
CE
tCHZ(1) tCOH
tRHZ(1) tRHOH(2)
Dout
R/B
NOTES : 1. Transition is measured at 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 2. tRLOH is valid when frequency is higher than 20MHz. tRHOH starts to be valid when frequency is lower than 20MHz.
Status Read Cycle
tCLR CLE tCLS tCS CE tCH tWP WE tWHR RE tDS I/Ox tDH tIR tREA tRHZ tRHOH Status Output tCEA tCHZ tCOH tCLH
70h/F1h
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Read Operation
tCLR CLE
Preliminary FLASH MEMORY
CE tWC WE tWB tAR ALE tR RE tRR I/Ox
00h
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
tCSD
tRC
tRHZ
30h
tCHZ tCOH
Dout N+2
Dout N Dout N+1 Dout M
Column Address
Row Address Busy
R/B
Read Operation(Intercepted by CE)
tCLR CLE
CE tCSD WE tWB tAR ALE tR RE tRR I/Ox
00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 30h
tRC
Dout N
Dout N+1
Column Address
Row Address
R/B
Busy
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Random Data Output In a Page
CLE tCLR
K9L8G08U1A K9G4G08U0A K9G4G08B0A
CE
WE
tWB
tAR tRC
tRHW
tWHR
23 tR tRR
Row Add1 Row Add2 Row Add3
ALE tREA
RE
I/Ox
Row Address
00h Dout N
Col. Add1
Col. Add2
30h
Dout N+1
05h
Col Add1
Col Add2
E0h
Dout M
Dout M+1
Column Address
Column Address
Preliminary FLASH MEMORY
R/B
Busy
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Page Program Operation
Preliminary FLASH MEMORY
CLE
CE
WE tADL ALE tWB tPROG tWHR
RE
Din Din N M 1 up to 2112 Byte Serial Input
I/Ox
80h
tWC
tWC
tWC
Co.l Add1 Col. Add2
Row Add1
Row Add2 Row Add3
10h Program Command
70h Read Status Command
I/O0
SerialData Column Address Input Command
Row Address
R/B
I/O0=0 Successful Program I/O0=1 Error in Program
NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
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Page Program Operation with Random Data Input
K9L8G08U1A K9G4G08U0A K9G4G08B0A
CLE
CE
WE tADL tADL
tWC tWC
tWC
tWB
tPROG
tWHR
Serial Data Column Address Input Command Row Address Serial Input
Random Data Column Address Input Command
Serial Input
Col. Add2
25
Row Add2 Row Add3
ALE
RE
I/Ox
80h 85h
Col. Add1
Col. Add2
Row Add1
Di Din N N Din M
Col. Add1
Din J
Din K
10h Program Command
70h Read Status Command
I/O0
R/B
I/O0=0 Successful Program I/O0=1 Error in Program
Preliminary FLASH MEMORY
NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
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Block Erase Operation
Preliminary FLASH MEMORY
CLE
CE tWC WE tWB ALE tBERS tWHR
RE
I/Ox
60h
Row Add1
Row Add2 Row Add3
D0h
70h
I/O 0
Row Address
Auto Block Erase Setup Command
Erase Command
R/B
Busy
Read Status Command
I/O0=0 Successful Erase I/O0=1 Error in Erase
26
Two-Plane Read Operation with Two-Plane Random Data Out
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CLE
CE
tW tWC
tW tWC
WE
tWB tR
K9L8G08U1A K9G4G08U0A K9G4G08B0A
ALE
RE
60h
A12~A19 A20~A27 A28~A29
I/Ox
Row Address
60h 30h
A12~A19 A20~A27 A28~A29
Row Address
R/B
A12 ~ A18 : Fixed 'Low' : Fixed 'Low' A19 A20 ~ A29 : Fixed 'Low' A12 ~ A18 : Valid : Fixed 'High' A19 A20 ~ A29 : Valid
Busy
1
27 tCLR
tW tWC
CLE
tCLR
CE
tW tWC
WE
tWHR tREA tRHW tRC
tWHR tREA tRC
ALE
RE
05h
A0~A7 A8~A11
I/Ox
Column Address
00h
A0~A7
A8~A11 A12~A19 A20~A27 A28~A29
E0h
Dout N
Dout N+1
00h
A0~A7
A8~A11 A12~A19 A20~A27 A28~A29
05h
Column Address Row Address
A0~A7
A8~A11
E0h
Column Address
Dout M
Dout M+1
Column Address Row Address
A0 ~ A11
:
Valid
A0 ~ A11 A0 ~ A11 : Fixed 'Low' A12 ~ A18 : Fixed 'Low' A19 : Fixed 'High' A20 ~ A29 : Fixed 'Low'
:
Valid
R/B
Preliminary FLASH MEMORY
1
A0 ~ A11 : Fixed 'Low' A12 ~ A18 : Fixed 'Low' : Fixed 'Low' A19 A20 ~ A29 : Fixed 'Low'
Two-Plane Page Program Operation
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CLE
CE

tDBSY
tWC
WE
tWB tWB tPROG tWHR
K9L8G08U1A K9G4G08U0A K9G4G08B0A
ALE
RE
I/Ox
80h 81h
A0~A7 A8~A11 A12~A19 A20~A27 A28~A29
A0~A7
A8~A11
A12~A19
A20~A27 A28~A29
Din N Din M 11h
Din N
Din M
10h Program Confirm Command (True)
70h/F1h Read Status Command
I/O 0
I/O0=0 Successful Program I/O0=1 Error in Program
28
tDBSY : typ. 500ns max. 1s
Serial Data Column Address Input Command
Program Page Row Address 1 up to 2112 Byte Data Command (Dummy) Serial Input
R/B
Ex.) Two-Plane Page Program tDBSY tPROG
R/B
I/O0~7
Address & Data Input A0 ~ A11 : Valid A12 ~ A18 : Fixed 'Low' : Fixed 'Low' A19 A20 ~ A29: Fixed 'Low'
80h
11h Note
81h
Address & Data Input A0 ~ A11 : A12 ~ A18 : A19 : A20 ~ A29 : Valid Valid Fixed 'High' Valid
Preliminary FLASH MEMORY
10h
70h/F1h
Note: Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
Two-Plane Block Erase Operation
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CLE
CE tWC
tWC
WE tWB tBERS tWHR
K9L8G08U1A K9G4G08U0A K9G4G08B0A
ALE
RE
I/OX
60h Row Address
Row Add1 Row Add2 Row Add3
60h D0h
Row Add1 Row Add2 RowD0h Add3
70h/F1h
I/O 0
29
Busy
Block Erase Setup Command2 Erase Confirm Command I/O 0 = 0 Successful Erase I/O 0 = 1 Error in Erase Read Status Command
Row Address
R/B
Block Erase Setup Command1
Ex.) Address Restriction for Two-Plane Block Erase Operation tBERS
60h Row Add1,2,3 A12 ~ A18 : Fixed 'Low' : Fixed 'High' A19 A20 ~ A29 : Valid D0h ~ A25 A9Address D0h 70h/F1h
R/B
I/O0~7
60h
Address
Row Add1,2,3
Preliminary FLASH MEMORY
A12 ~ A18 : Fixed 'Low' : Fixed 'Low' A19 A20 ~ A29 : Fixed 'Low'
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Read ID Operation
CLE
Preliminary FLASH MEMORY
CE
WE tAR ALE
RE tREA I/Ox
90h Read ID Command 00h Address. 1cycle ECh Device Code 3rd cyc. 4th cyc. 5th cyc.
Maker Code Device Code
Device K9G4G08B0A K9G4G08U0A K9L8G08U1A
Device Code(2nd Cycle) DCh DCh
3rd Cycle 14h 14h
4th Cycle 25h 25h
5th Cycle 54h 54h
Same as each K9G4G08U0A in it
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ID Definition Table 90 ID : Access command = 90H
Description 1 Byte 2nd Byte 3rd Byte 4th Byte 5th Byte
st
Preliminary FLASH MEMORY
Maker Code Device Code Internal Chip Number, Cell Type, Number of Simultaneously Programed Pages, etc Page Size, Block Size, Redundant Area Size, Organization, Serial Access Minimum Plane Number, Plane Size
3rd ID Data
Description 1 2 4 8 2 Level Cell 4 Level Cell 8 Level Cell 16 Level Cell 1 2 4 8 Not Support Support Not Support Support 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 0 0 1 1 0 1 0 1
Internal Chip Number
Cell Type
Number of Simultaneously Programmed Pages Interleave Program Between multiple chips Cache Program
4th ID Data
Description Page Size (w/o redundant area ) 1KB 2KB 4KB 8KB 64KB 128KB 256KB 512KB 8 16 x8 x16 50ns/30ns 25ns Reserved Reserved 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 0 0 1 1 0 1 0 1
Block Size (w/o redundant area ) Redundant Area Size ( byte/512byte) Organization
Serial Access Minimum
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5th ID Data
Description 1 2 4 8 64Mb 128Mb 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 I/O7 I/O6 I/O5 I/O4
Preliminary FLASH MEMORY
I/O3 I/O2 0 0 1 1 0 1 0 1
I/O1
I/O0
Plane Number
Plane Size (w/o redundant Area)
Reserved
0
0
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Device Operation
PAGE READ
Preliminary FLASH MEMORY
Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data within the selected page are transferred to the data registers in less than 60s(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 30ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address. The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated multiple times regardless of how many times it is done in a page.
Figure 6. Read Operation
CLE CE WE ALE R/B RE I/Ox
00h Address(5Cycle) Col Add1,2 & Row Add1,2,3 30h Data Output(Serial Access)
tR
Data Field
Spare Field
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Figure 7. Random Data Output In a Page
R/B RE I/Ox
00h Address 5Cycles 30h Data Output 05h Address 2Cycles
Preliminary FLASH MEMORY
tR
E0h
Data Output
Col Add1,2 & Row Add1,2,3
Data Field
Spare Field
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, and the number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 1 time for the page. The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 2,112bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and then serial data loading. The data other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page. The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register.
Figure 8. Program & Read Status Operation
tPROG R/B
"0"
I/Ox
80h
Address & Data Input Col Add1,2 & Row Add1,2,3 Data
10h
70h
I/O0 "1" Fail
Pass
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Figure 9. Random Data Input In a Page
tPROG R/B
Preliminary FLASH MEMORY
"0"
I/Ox
80h
Address & Data Input Col Add1,2 & Row Add1,2,3 Data
85h
Address & Data Input Col Add1,2 Data
10h
70h
I/O0 "1" Fail
Pass
Table 2. Paired Page Address Information
Paired Page Address 00h 02h 06h 0Ah 0Eh 12h 16h 1Ah 1Eh 22h 26h 2Ah 2Eh 32h 36h 3Ah 3Eh 42h 46h 4Ah 4Eh 52h 56h 5Ah 5Eh 62h 66h 6Ah 6Eh 72h 76h 7Ah 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h 48h 4Ch 50h 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch 7Eh 01h 03h 07h 0Bh 0Fh 13h 17h 1Bh 1Fh 23h 27h 2Bh 2Fh 33h 37h 3Bh 3Fh 43h 47h 4Bh 4Fh 53h 57h 5Bh 5Fh 63h 67h 6Bh 6Fh 73h 77h 7Bh Paired Page Address 05h 09h 0Dh 11h 15h 19h 1Dh 21h 25h 29h 2Dh 31h 35h 39h 3Dh 41h 45h 49h 4Dh 51h 55h 59h 5Dh 61h 65h 69h 6Dh 71h 75h 79h 7Dh 7Fh
Note: When program operation is abnormally aborted (ex. power-down), not only page data under program but also paired page data may be damaged(Table 2).
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BLOCK ERASE
Preliminary FLASH MEMORY
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only address A19 to A29 is valid while A12 to A18 is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 10 details the sequence.
Figure 10. Block Erase Operation
R/B tBERS
"0"
I/Ox
60h
Address Input(3Cycle) Row Add. : A12 ~ A29
D0h
70h
I/O0 "1" Fail
Pass
Two-Plane Read
Two-Plane Read is an extension of Read, for a single plane with 2,112 byte page registers. Since the device is equipped with two memory planes, activating the two sets of 2,112 byte page registers enables a random read of two pages. Two-Plane Read is initiated by repeating command 60h followed by three address cycles twice. In this case only same page of same block can be selected from each plane. After Read Confirm command(30h) the 4,224 bytes of data within the selected two page are transferred to the data registers in less than 60us(tR). The system controller can detect the completion of data transfer(tR) by monitoring the output of R/B pin. Once the data is loaded into the data registers, the data output of first plane can be read out by issuing command 00h with Five Address Cycles, command 05h with two column address and finally E0h. The data output of second plane can be read out using the identical command sequences. The restrictions in addressing with Two-Plane Read are shown in Figure 11. Two-Plane Read must be used in the block which has been programmed with Two-Plane Page Program.
Figure 11. Two-Plane Page Read Operation with Two-Plane Random Data Out
R/B I/OX tR
60h
Address (3 Cycle) Row Add.1,2,3 A12 ~ A18 : Fixed 'Low' : Fixed 'Low' A19 A20 ~ A29 : Fixed 'Low'
60h
Address (3 Cycle) Row Add.1,2,3 A12 ~ A18 : Valid : Fixed 'High' A19 A20 ~ A29 : Valid
30h
1
R/B I/Ox 1
00h Address (5 Cycle) 05h Address (2 Cycle) Col. Add.1,2 A0 ~ A11
:
E0h
Data Output
Col. Add. 1,2 & Row Add.1,2,3 A0 ~ A11 : Fixed 'Low' A12 ~ A18 : Fixed 'Low' : Fixed 'Low' A19 A20 ~ A29 : Fixed 'Low'
Valid
2
R/B I/Ox 2
00h Address (5 Cycle) 05h Address (2 Cycle) Col. Add.1,2 A0 ~ A11
:
E0h
Data Output
Col. Add. 1,2 & Row Add.1,2,3 A0 ~ A11 : Fixed 'Low' A12 ~ A18 : Fixed 'Low' : Fixed 'High' A19 A20 ~ A29 : Fixed 'Low'
Valid
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Two-Plane Page Program
Preliminary FLASH MEMORY
Two-Plane Page Program is an extension of Page Program, for a single plane with 2112 byte page registers. Since the device is equipped with two memory planes, activating the two sets of 2112 byte page registers enables a simultaneous programming of two pages. After writing the first set of data up to 2112 byte into the selected page register, Dummy Page Program command (11h) instead of actual Page Program command(10h) is inputted to finish data-loading of the first plane. Since no programming process is involved, R/B remains in Busy state for a short period of time(tDBSY). Read Status command (70h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set of data for the other plane is inputted after the 81h command and address sequences. After inputting data for the last plane, actual True Page Program command(10h) instead of dummy Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the same as that of Page Program. Status bit of I/O 0 is set to "1" when any of the pages fails. Restriction in addressing with TwoPlane Page Program is shown in Figure12.
Figure 12. Two-Plane Page Program
R/B I/O0 ~ 7 tDBSY tPROG
80h
Address & Data Input A0 ~ A11 : Valid A12 ~ A18 : Fixed 'Low' : Fixed 'Low' A19 A20 ~ A29: Fixed 'Low'
11h Note2
81h
Address & Data Input A0 ~ A11 : A12 ~ A18 : : A19 A20 ~ A29 :
"0" 10h 70h/F1h I/O0 "1" Fail Pass
Valid Valid Fixed 'High' Valid
NOTE : 1. It is noticeable that physically same row address is applied to two planes . 2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh. 80h 11h 81h 10h
Data Input
Plane 0 (1024 Block)
Plane 1 (1024 Block)
Block 0 Block 2
Block 1 Block 3
Block 2044 Block 2046
Block 2045 Block 2047
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Two-Plane Block Erase
Preliminary FLASH MEMORY
Basic concept of Two-Plane Block Erase operation is identical to that of Two-Plane Page Program. Up to two blocks, one from each plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command(60h) followed by three address cycles) may be repeated up to twice for erasing up to two blocks. Only one block should be selected from each plane. The Erase Confirm command(D0h) initiates the actual erasing process. The completion is detected by monitoring R/B pin or Ready/ Busy status bit (I/O 6).
Figure 13. Two-Plane Erase Operation
R/B I/OX tBERS
"0" I/O0 "1" Fail Pass
60h
Address (3 Cycle) A12 ~ A18 : Fixed 'Low' : Fixed 'Low' A19 A20 ~ A29 : Fixed 'Low'
60h
Address (3 Cycle) A12 ~ A18 : Fixed 'Low' : Fixed 'High' A19 A20 ~ A29 : Valid
D0h
70h/F1h
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READ STATUS
Preliminary FLASH MEMORY
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h or F1h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to Table 3 for specific 70h Status Register definitions and Table 4 for for specific F1h Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read cycles.
Table 3. 70h Read Status Register Definition
I/O No. I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Page Program Pass/Fail Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Block Erase Pass/Fail Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Read Not use Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Pass : "0" Don't -cared Don't -cared Don't -cared Don't -cared Don't -cared Busy : "0" Protected : "0" Ready : "1" Not Protected : "1" Definition Fail : "1"
NOTE : 1. I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed.
Table 4. F1h Read Status Register Definition
I/O No. I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Page Program Chip Pass/Fail Plane0 Pass/Fail Plane1 Pass/Fail Not Use Not Use Not Use Ready/Busy Write Protect Block Erase Chip Pass/Fail Plane0 Pass/Fail Plane1 Pass/Fail Not Use Not Use Not Use Ready/Busy Write Protect Read Not use Not use Not use Not Use Not Use Not Use Ready/Busy Write Protect Pass : "0" Pass : "0" Pass : "0" Don't -cared Don't -cared Don't -cared Busy : "0" Protected : "0" Ready : "1" Not Protected : "1" Definition Fail : "1" Fail : "1" Fail : "1"
NOTE : 1. I/Os defined 'Not use' are recommended to be masked out when Read Status is being executed.
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K9L8G08U1A K9G4G08U0A K9G4G08B0A
Read ID
Preliminary FLASH MEMORY
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd cycle ID, 4th cycle ID, 5th cycle ID respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence.
Figure 14. Read ID Operation
CLE CE WE tAR ALE RE tWHR I/OX
90h 00h Address. 1cycle
tCLR tCEA
tREA
ECh Maker code
Device Code Device code
3rd Cyc.
4th Cyc.
5th Cyc.
Device K9G4G08B0A K9G4G08U0A K9L8G08U1A
Device Code(2nd Cycle) DCh DCh
3rd Cycle 14h 14h
4th Cycle 25h 25h
5th Cycle 54h 54h
Same as each K9G4G08X0A in it
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to Table 5 for device status after reset operation. If the device is already in reset state a new reset command will be accepted by the command register. The R/B pin changes to low for tRST after the Reset command is written. Refer to Figure 15 below.
Figure 15. RESET Operation
tRST R/B I/OX
FFh
Table 5. Device Status
After Power-up Operation mode 00h Command is latched After Reset Waiting for next command
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K9L8G08U1A K9G4G08U0A K9G4G08B0A
READY/BUSY
Preliminary FLASH MEMORY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 16). Its value can be determined by the following guidance.
Rp VCC
ibusy 2.7V device - VOL : 0.4V, VOH : Vcc-0.4V 3.3V device - VOL : 0.4V, VOH : 2.4V VOH
Ready Vcc R/B open drain output
CL
VOL Busy tf tr
GND Device
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K9L8G08U1A K9G4G08U0A K9G4G08B0A
Preliminary FLASH MEMORY
Figure 16. Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 2.7V, Ta = 25C , CL = 30pF
2.3
200n
tr,tf [s]
Ibusy
2m
1.1
Ibusy [A]
120 90
100n tr
30 2.3 60
1m
0.55 2.3
0.75 2.3
tf
2.3
1K
2K 3K Rp(ohm)
4K
@ Vcc = 3.3V, Ta = 25C , CL = 50pF
2.4
200n
tr,tf [s]
Ibusy
150 1.2
200
2m
Ibusy [A]
100n tr
50 3.6
100
0.8 0.6
1m
tf
3.6
3.6
3.6
1K
2K 3K Rp(ohm)
4K
Rp value guidance
Rp(min, 2.7V part) = VCC(Max.) - VOL(Max.) IOL + IL VCC(Max.) - VOL(Max.) IOL + IL = = 2.4V 3mA + IL 3.2V 8mA + IL
Rp(min, 3.3V part) =
where IL is the sum of the input currents of all devices tied to the R/B pin. Rp(max) is determined by maximum permissible limit of tr
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K9L8G08U1A K9G4G08U0A K9G4G08B0A
Data Protection & Power up sequence
Preliminary FLASH MEMORY
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.8V(2.7V device), 2V(3.3V device). WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 100s is required before internal circuit gets ready for any command sequences as shown in Figure 17. The two step command sequence for program/erase provides additional software protection.
Figure 17. AC Waveforms for Power Transition
2.7V device : ~ 2.0V 3.3V device : ~ 2.5V VCC High
2.7V device : ~ 2.0V 3.3V device : ~ 2.5V
WP
WE
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100s
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K9L8G08U1A K9G4G08U0A K9G4G08B0A
nWP AC Timing guide
Enabling nWP during erase and program busy is progibited. The erase and program operations are enabled and disabled as follows:
Preliminary FLASH MEMORY
Figure 18. Program Operation
1. Enable Mode nWE I/O nWP RnB tww(min.100ns) 80h
10h 80h
2. Disable Mode nWE I/O nWP RnB tww(min.100ns)
10h 60h
Figure 19. Erase Operation
1. Enable Mode nWE I/O nWP RnB tww(min.100ns)
D0h 60h
2. Disable Mode nWE I/O nWP RnB tww(min.100ns)
D0h
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